mize the number of measured profiles.
A profile is made up of range samples
digitized along the laser line on the part
surface. The decision to capture profiles
surrounding the nozzle for processing
surface and bead information meant
four lasers each sampling 1000 pps for a
bandwidth of 4000 pps total. This speed
goal was exceeded by ensuring that the
combined pixel rate of the four imagers
was supported by the entire system.
Fundamentally, the acquisition rate
should only be limited by the pixel rate
of the imager. Raw pixel data races out
of the imagers via high-speed serial-
ized low-voltage differential signaling
(LVDS) channels. The FPGA has dedi-
cated resources to handle LVDS deseri-
alization and inter-channel synchroniza-
tion at the highest pixel rates. Reference
design blocks are available from either
the FPGA or image sensor vendor and
can be integrated with application-
specific FPGA code.
The FPGA interface to CPU memory
via direct memory access (DMA) has a
finite bandwidth. The tradeoff between
acquisition rate (pps) and bead height (
inspection depth range = number of image
lines readout per image) pivots about the
bandwidth of this interface. It also may
be limited by image exposure time to
achieve required laser image SNR for
reliable image processing. Therefore, the
dominant system trade-off is between
speed, bead height and SNR.
In practice, two of these three constraints will limit the system profile sampling speed. If a certain application has a
tall bead, then a larger imager window
that reduces pps must be used. The larger
window increases both the readout time
from the imager and the required PCIe
bandwidth to transfer the images.
Finally, the application engine must be
capable of accessing and processing bead
profile shapes at high rates and, on aver-
age, not fall behind the vision engine ac-
quisition rate. The circular image buffer
in CPU memory provides some elastic-
ity but, ultimately, the acquisition speed
may be limited by the processing speed.
The highest speeds are achieved with
a combination of a SoM with the latest
multicore processor, intelligent memory
management and highly optimized algo-
High-speed and high-fidelity 3D inspection of adhesive beads can be
achieved in a compact, robust, flexible,
embedded vision design. Higher bandwidth and low cost goals can be met on
an individual application basis by using
more sophisticated (or economical)
SoMs and FPGAs that support faster
(or slower) DMA interfaces. This results
in highly tailored solutions that are scalable and low cost.
Meet the authors
Dave Kelly is vice president of research and
development at Coherix Inc., with more than
25 years’ experience developing embedded
vision systems for industrial and military applications; email: firstname.lastname@example.org.
Andres Tamez is an embedded specialist and electronics manager at Coherix Inc.;
22 Industrial Photonics July 2017 www.IndPhotonics.com
➤ 3D Bead Inspection
The embedded design integrating FPGA, PIC32, SoM, imagers and lasers supports,
high speeds, low latency and application-specific operation scenarios. This diagram
shows the connections for timing, data, I/O and power.